Integrated circuits (ICs) often contain millions of transistors and millions of interconnections. To verify that these transistors and interconnections operate as intended, they must be tested. Many testing techniques may be used to verify the operation of an IC.
For example, broadside testing includes electrically stimulating the inputs of an IC and measuring the outputs of the IC to determine if the output matches the predicted output. In the case where the predicted output matches the measured output, the IC may be functioning correctly. However, this test alone does not guarantee that the IC will function 100 percent correctly. More tests are needed to verify that the IC is operating as designed.
In the case where broadside testing is used and the measured output does not match the predicted output, the IC may not be operating correctly. This type of testing indicates that there may be problems with the IC. However, this type of testing usually does not indicate what in particular caused the IC to operate incorrectly. To better diagnose what may be causing the IC to fail, delay fault testing may be used.
Delay fault testing or “at-speed” testing is a test methodology used to measure the time required for a signal to travel through a block of circuits (e.g. logic, memory etc.) on an integrated circuit. This time is often called the delay time Td. Usually, the frequency F at which an integrated circuit may operate is determined by the longest delay time Td on the integrated circuit. In this case, the highest clock frequency that the integrated circuit may operate is F=1/Td.
Integrated circuits often have more than one clock domain. Each clock domain may operate at a different frequency from the other clock domains. Distributed clock dividers as shown in FIG. 1 are used to provide the clock frequencies CLK1, CLK2, CLK3, ClK4 needed for each clock domain. In this example, a full speed clock CLK is provided by a phase-locked loop (PLL) 110 to each distributed clock dividers 102, 104, 106 and 108. A divide ratio DR1, DR2, DR3 and DR3 is provided to each distributed clock divider 102, 104, 106 and 108 respectively. The divide ratio determines the frequency of the clocks CLK1, CLK2, CLK3 and CLK4 output by the distributed clock dividers 102, 104, 106 and 108 respectively. Clocks CLK1, CLK2, CLK3 and CLK4 are used to provide clocks to circuits in clock domains 112, 114, 116 and 118 respectively.
Delay times Td need to be measured in each clock domain 112, 114, 116 and 118 in order to fully test an integrated circuit. The control of these tests may be accomplished by the use of an on-chip test control circuit. In an embodiment of the invention, the on-chip test control circuitry sends code to each clock domain 112, 114, 116 and 118. In this embodiment, the code sent to each of the distributed clock dividers 102, 104, 106 and 108 selects the type of distributed clock divider used and the delays between the pulses needed to delay fault test clock domains on an integrated circuit.